On die Low Drop-Out (LDO) regulator is emerging as a strong candidate to enable fine-grain voltage domains, where logic blocks of the same or different functionality, for example, execution units within a graphics core, or different logic blocks within a system on chip (SOC), have the autonomy to run at different frequency and supply levels (Vcc) at different times depending on workload needs and/or minimum operating voltage (Vmin) limits. An LDO can provide relatively high current density with a small area overhead compared to other bulkier Integrated Voltage Regulators (IVRs) like Switched-capacitor Voltage regulators (SCVRs) and inductor-based buck converters.
However, conventional LDOs use an analog amplifier for voltage monitoring and feedback control, making it less favorable to supply voltage and technology scaling. Furthermore, loop stability requirement (of the feedback) and power budget often set a limit on the bandwidth of the conventional LDO, thus degrading the voltage regulation to large load transients.
When multiple conventional LDOs are connected to the same power grid (of a large voltage domain), non-idealities like offsets (amongst conventional LDO amplifiers, for example) can cause current crowding in certain logical sub-blocks, incurring reliability concerns and LDO performance degradation. Furthermore, interaction between conventional LDO blocks via the power grid complicates stability analysis under various load conditions and process temperature, and voltage (PVT) variations.